The present invention relates to a method of manufacturing a semiconductor device (or a semiconductor integrated circuit device), and particularly to a technique useful in application to a resin molding technique.
Japanese Unexamined Patent Publication No. JP-A-2010-263066 relates to resin seal techniques such as QFP (Quad Flat Package), and QFN (Quad Flat Non-Leaded Package). Therein disclosed is a technique for providing a recess part in a gate insert piece in order to prevent an inner lead in a corner part from being deformed as a result of the concentration of a clamp pressure by a gate insert piece (Gate Insert Piece) of a mold.
JP-A-2001-320007, and U.S. Pat. No. 6,744,118 which is a counterpart thereof relate to a single-side collective mold in which a lead frame is used. Therein disclosed is a technique for performing half-etching on a tie-bar portion of a boundary portion between unit device regions to avoid various problems involved in package dicing.